A memory cell in an integrated circuit, such as a dynamic random access memory (DRAM) array, typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device, such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to either apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is proportional to the capacitance, C=kk0A/d, where k is the dielectric constant of the capacitor dielectric, k0 is the vacuum permittivity, A is the electrode area and d is the spacing between the electrodes.
As the packing density of memory cells continues to increase, each capacitor must still maintain a certain minimum charge storage to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge per footprint or unit of chip area occupied.
An integrated capacitor generally has a bottom electrode plate, or a storage electrode, and a top electrode plate, or a reference electrode, separated by a dielectric layer. Several techniques have recently been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These techniques include increasing the effective surface area of both the storage and reference electrodes by creating folding structures such as those in trench, stack or container capacitors. Such structures better utilize the available chip area by creating three-dimensional shapes to which the conductive electrodes and capacitor dielectric conform. The surface of the electrodes may be further increased by providing a roughened surface to the bottom electrode over which the capacitor dielectric and the top electrode are conformally deposited.
A container capacitor, for example, as shown in FIG. 1, can be formed on top of a semiconductor substrate 100, over MOS transistors 101, 103 fabricated with and upon the substrate 100. A layer of dielectric material 107 is deposited on top of the transistors 101, 103, and a conductive plug 108 is formed through the dielectric. After a process of chemical-mechanical polishing (CMP), another layer of dielectric material 110 is deposited. A container-shaped opening 112 is then formed through the layer 110 to expose the conductive plug 108. A layer of conductive material 114 is then deposited onto the structure to serve as the bottom electrode plate of the capacitor. The material 114 is then polished by another CMP process to isolate capacitors across the array from each other, leaving the film 114 inside the container. A capacitor dielectric layer 116 is then formed, followed by deposition of a top electrode plate 118.
In order to further increase the capacitance of the capacitors, other techniques concentrate on the use of new dielectric materials having a higher dielectric constant “k”, often referred to as high-k materials. Such materials include tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (ST), barium titanate (BT), lead zirconium titanate (PZT) and strontium bismuth tantalate (SBT). The effective dielectric constants of these materials are significantly higher than conventional dielectrics (e.g., silicon oxides and nitrides). For example, the dielectric constant of silicon oxide is about 3.9, and the dielectric constant of the new materials can range from 20 to 40 for Ta2O5, up to 300 for BST; the dielectric constants of some materials can be even higher (600 to 800). Using such materials enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement, enabling the packing density dictated by current and future circuit designs.
Difficulties have been encountered, however, in incorporating these materials into fabrication process flows. For example, Ta2O5, is deposited by chemical vapor deposition (CVD) employing organometallic precursors in a highly oxidizing ambient environment. After deposition, the material is typically annealed to remove carbon. This annealing process is typically conducted in the presence of oxidizing agents, such as oxygen (O2), ozone (O3) or nitrous oxide (N2O or NO), while volatile carbon complexes are driven out.
Due to the volatility of the reactants and by-products of processes for forming high k materials, surrounding materials are subject to degradation. For example, when the bottom electrode plate is made of metal or polycrystalline silicon (polysilicon), which is connected by a polysilicon or tungsten plug to the silicon substrate, all these materials can be oxidized during the deposition and anneal of the high k material. Although electrodes can be made of noble metals, such as platinum, where the noble metals are not easily oxidized, oxygen can still diffuse through the metal electrodes. Therefore, the surrounding oxidizable materials, including the polysilicon plug and the silicon substrate below, are still subject to degradation.
Oxidation of the electrode, the underlying polysilicon plug or the underlying substrate reduces conductivity of these electrical elements, while oxidation of electrode surfaces adjacent the dielectric reduces cell capacitance due to the formation of a layer of oxide with a relatively low dielectric constant. These problems have been viewed as major obstacles to incorporating high k materials into integrated circuits. Past efforts have therefore focused on using highly conductive diffusion barriers as the bottom electrode plate between the high dielectric material and the oxidizable elements, such as polysilicon plugs.
In order to solve the above problems in making a high-k capacitor, highly conductive metal oxides, such as ruthenium oxide (RuOx) and iridium oxide (IrOx) have been used to form the electrode plates. Such oxides are not corroded by oxidizing atmospheres, making them favorable candidates in avoiding the aforementioned electrode oxidation problem. At the same time, their barrier function can prevent the oxidation of underlying conductive plugs.
However, existing processes for fabricating RuOx/high-k container capacitors with the structure of FIG. 1 has some disadvantages. FIGS. 2A-2D illustrate conventional process steps, and, for the purpose of simplicity, the drawings only show the capacitor container without showing the underlying devices, such as the substrate, the transistors and the conductive plugs.
Referring to FIG. 2A, a crystallized RuOx, film 214 is normally deposited onto the container shaped structure 112 and 110 by using chemical vapor deposition or sputtering deposition. The film 214 can be deposited at high temperatures to form a crystalline film 214 with high conductivity. Unfortunately, a high temperature deposition reduces conformality, as shown in FIG. 2A, where the RuOx, film 214 is thicker at the top rim 220 of the container and thinner at the bottom corner 222. This undesirable configuration will often cause discontinuities in the film 214. Thus, the process margin is limited, especially for circuit designs in which conformal dielectrics are needed.
Referring to FIG. 2B, a chemical mechanical polishing (CMP) process is carried out to polish off the portion of RuOx, film overlying the dielectric 110, leaving a portion 214′ inside the container 112. The CMP process, however, can not be efficiently carried out due to the extreme hardness of the crystallized RuOx film 214. The difficulty of the CMP adversely affects the throughput of the fabrication. Also, because of the non-uniformity of the film deposition, CMP leaves a sharp corner 220′ at the top portion of the film. Thus, when the next layer of a high-k dielectric material 216 is deposited, as shown in FIG. 2C, the non-ideal conformality of the structure can cause a fatal defect of the device, especially at the thinning point 224. If the dielectric layer is too thin at this point, the capacitor can be leaky, or even shorted.
Referring to FIG. 2D, a top electrode layer is then deposited on the high-k dielectric. Again, due to imperfect conformality in the previously formed dielectric, there may be a void left inside the container. As is known in the art, such voids can trap moisture and thereby reduce device lifespan.
There is thus a need for a fabrication method of a high-k/metal oxide container capacitor with improved structure conformality and uniformity, which will increase the total capacitance while minimizing leakage of the capacitor.